1. Field of the Invention
The invention relates to computing systems and, more particularly, to an efficient implementation of timers in a multithreaded processing system.
2. Description of the Related Art
Microprocessors and other processing devices frequently include mechanisms for controlling the scheduling of processes and access to resources in general. Because multiple processes may be executing within a given device, or may otherwise be seeking access to a limited number of resources, it is often desirable or necessary to implement some type of timesharing mechanism in order to allow the processes shared access according to some particular schedule. Due to the nature of timesharing and other scheduling mechanisms, timers are frequently utilized to provide software a simple mechanism for controlling the scheduling processes. For example, in a simple uniprocessor system, prior to scheduling the execution of a particular process by the processor, a supervisor (e.g., an operating system component) or other control program may set a timer which controls how long the process may run before control is returned from the processor to the operating system. By maintaining control over how long processes may run, the operating system or other control program can time multiplex use of the processor between multiple processes in a controlled manner.
Some software models provide for multiple levels of supervisors. For example, some software models may utilize an intermediate layer between the hardware and one ore more supervisors. In this manner the hardware layer is abstracted from the supervisor or operating system. In some models this intermediate layer may be referred to as the hypervisor. The supervisor then runs under the control of the hypervisor and user programs run under the control of the supervisor. In such a model, not only may a particular supervisor time multiplex processes on a given processor, but multiple supervisors may also be time multiplexed. Consequently, multiple levels of time multiplexing may exist within a given system.
In order to support multiple levels of time multiplexing, a processor may include multiple timers. One timer may provide the ability of a hypervisor to regain control from a supervisor. Another timer may provide the ability of the supervisor to regain control from a user program. Still other timers may be used by user programs or for other reasons. Typically, each of these timers are implemented by comparing a value in a dedicated register to a reference clock or counter of some sort. The typical reference counter may simply be a register whose value is incremented every processor cycle. A typical implementation of each additional timer may be a second register (the “compare” register) that feeds a comparator. The comparator compares the contents of the compare register with the current state of the reference counter.
One problem with the above described approach is that the number of compare registers increases with the number of software layers. For example, in the hypervisor—supervisor—user model, each level normally has its own compare register even though they may all share the same reference counter. In addition, each compare register typically has its own comparator. Further, if a processor is configured to execute more than a single thread, each of these timers must generally be implemented for each thread and the total number of timers may rapidly grow to a relatively large number.
Accordingly, an efficient mechanism for implementing timers is a computing system is desired.